This disclosure relates generally to the field of chip design. More particularly, this disclosure relates to techniques for timing analysis of repeated blocks.
Semiconductor chips can be composed of complex electronic circuit arrangements. With each progressive generation of semiconductor technology, the number of components on a single chip may exponentially increase. The number of devices found on a chip, as well as their close proximity, can drive significant effort in analysis. One key aspect of analysis may be the determination of relative delays. Another may be ensuring that all timing requirements can be met on chip. Yet another may be implementing the layout of all the devices on chip. The relative placement of the devices can require significant computation resources, as each cell must be selected, placed, and routed to across the entire chip.
Often times, a soft macro or block can be implemented more than once on chip. These multiple instances can be referred to as repeated blocks. If each instance of a repeated block is implemented independently, then the different timing and layout optimizations may cause the instances to be different. These differences may cause the implementation calculations, such as the timing analysis, to be repeated for each repeated instance of a repeated block. Additionally, the cell selection, placement, and associated routing all may be repeated for each instance of the repeated block. Therefore, all of these calculations can require computing resources and time, both of which may become a significant concern as chips become larger and more complex.
Furthermore, if the instances of a repeated block are all implemented independently, the differences can create debug problems, as each instance will likely have different properties. With independent implementations there may actually be problems where one instance would work and another instance would not work properly. Additionally, the differences between instances of repeated blocks can also be problematic whenever a modification is required in a repeated block. A modification, also often referred to as an Engineering Change Order (ECO), likely must be implemented on each and every instance. Moreover, verification also can become a problem for repeated blocks, since each verification step likely must be repeated on each instance.
Accordingly, what is desired are improved methods and apparatus for solving some of the problems discussed above. Additionally, what is desired are improved methods and apparatus for reducing some of the drawbacks discussed above.